1. Field of the Invention
This invention relates to an analog-to-digital converter, and more particularly to a successive approximation analog-to-digital converter.
2. Description of the Related Art
Among various types of analog-to-digital converters, a conventional successive approximation analog-to-digital converter can provide better energy efficiency and only dissipates dynamic power, and is therefore suitable for use under circumstances with limited power source. Since dissipation of dynamic power in the conventional successive approximation analog-to-digital converter is directly proportional to the square of its power supply voltage and to its capacitive loads, decreasing the power supply voltage and the capacitive loads can enhance energy efficiency. However, the conventional successive approximation analog-to-digital converter still has the following drawbacks when operating at low power supply voltage:
1. Deterioration of conversion accuracy attributed to input interference and leakage currents under a low operation speed of the conventional successive approximation analog-to-digital converter cannot be effectively solved.
2. When the power supply voltage is decreased, some circuits of the conventional successive approximation analog-to-digital converter may fail to perform appropriately, and the conventional successive approximation analog-to-digital converter may fail to complete conversion within a predetermined time period.
3. The control logic of the conventional successive approximation analog-to-digital is rather complex.